The present invention relates generally to integrated circuit comparators, and more particularly to ways of reducing average power consumption of high-speed comparators, and still more particularly to comparators including circuitry for adjusting comparator speed/propagation delay and comparator power consumption according to external system needs.
High speed (i.e., low signal propagation delay) of a comparator in a system may need to be adjusted according to the present operation requirements of the system. For example, the error comparator of a current mode DC-to-DC converter needs to be fast (e.g., with a propagation delay of 10-20 nanoseconds) when a power switch is ON, but the propagation delay may be 10-1000 times greater when the power switch is OFF. Reducing the power consumption of the comparator during time intervals when high speed (i.e., low propagation delay) is not needed may provide a substantial decrease in overall power consumption of a system containing comparators.
“Prior Art” FIG. 1 shows a comparator 1 that includes a differential input stage including N-channel input transistors M0 and M1 having their sources connected by conductor 2 to one terminal of a tail current source ITAIL, the other terminal of which is connected to VSS. The gates of transistors M0 and M1 are coupled to input signals VIN− and VIN+, respectively. The drain of input transistor M0 is connected by conductor 3 to the drain and gate of a P-channel load transistor M2, the gate of a P-channel “hysteresis” transistor M6, the drain of a P-channel “hysteresis” transistor M7, and the gate of a P-channel current mirror output transistor M4. The sources of transistors M2, M6, M7, and M4 are connected to VDD. Similarly, the drain of input transistor M1 is connected by conductor 4 to the drain and gate of a P-channel load transistor M3, the gate of P-channel “hysteresis” transistor M7, the drain of P-channel “hysteresis” transistor M6, and the gate of a P-channel current mirror output transistor M5. The source of transistor M5 is connected to VDD.
Diode-connected load transistor M2 functions as the input transistor of a first current mirror that also includes output transistor M4, and diode-connected load transistor M3 functions as the input transistor of a second current mirror that also includes output transistor M5. These two current mirrors form a second stage of comparator 1. The drain of current mirror output transistor M4 is connected by conductor 6 to the input of an output inverter or buffer 7, the drain of a N-channel transistor M8, and the gate of a N-channel transistor M9. The sources of transistors M8 and M9 are connected to VSS. Similarly, the drain of current mirror output transistor M5 is connected by conductor 5 to the drain of N-channel transistor M9 and the gate of N-channel transistor M8. Current mirror output transistors M4 and M5 and transistors M8 and M9 form a latch circuit that operates to latch the desired state of comparator 1. The circuitry including transistors M8 and M9 may be thought of as a third stage of comparator 1.
Transistors M6 and M7 provide hysteresis for comparator 1 in response to local positive feedback for hysteresis provided by latch transistors M8 and M9. For low current consumption, the third stage including latch transistors M8 and M9 latches the desired state of comparator 1. As a result, the quiescent current (Iq) of comparator 1 is equal to the tail current ITAIL of the input differential input stage including input transistors M0 and M1. (Comparator 1 in Prior Art FIG. 1 alternatively is sometimes implemented with transistors M8 and M9 functioning as a conventional current mirror utilized as a pair of load devices rather than as a latch circuit. The current mirror could include transistor M9 connected as a current mirror input transistor and transistor M8 connected as a current mirror output transistor. However, such a current mirror consumes twice as much current as the above described latch circuit M8/M9 because the current mirror input transistor and current mirror output transistor each conducts an amount of current equal to the tail current ITAIL.)
The above-mentioned hysteresis may be provided to avoid multiple parasitic switching of comparator 1. The input-referred hysteresis of comparator 1 is equal to 2Vth ln(N), where Vth=kT/q and N is the “area ratio” M2/M6=M3/M7, where M2/M6 represents the ratio of the W/L ratio of transistor M2 divided by the W/L ratio of transistor M6 (where “W” and “L” are the channel-width and channel-length, respectively, of the field effect transistor). Differentially coupled MOS input transistors M0 and M1 may be operated in their weak inversion regions to improve the power-speed ratio of the differential input stage.
The speed of comparator 1 is directly proportional to its tail current ITAIL, or, stated differently, the propagation delay of comparator 1 is inversely proportional to ITAIL. Comparator 1 in FIG. 1 typically has a high power-to-speed ratio, and its propagation delay is dominated by the amount of time required to charge the parasitic input capacitance of the second stage with the current produced by differential input stage M0/M1, and therefore is inversely proportional to ITAIL. The parasitic input capacitance of the second stage mainly includes the gate capacitances of current mirror output transistors M4 and M5.
The value of tail current ITAIL needs to be sufficiently high to ensure that the currents of current mirrors M2/M4 and M3/M5 are capable of switching the latch including transistors M8 and M9. Consequently, the minimum value of ITAIL is undesirably large for some applications, and therefore the variable range of the quiescent current (Iq) of comparator 1 is undesirably small. ITAIL needs to be sufficiently large to cause current mirror input transistors M2 or M3 to mirror enough current through current mirror output transistor M4 or M5, respectively, to overpower whichever of transistors M8 and M9 is presently turned on in order to cause the above mentioned latch circuit to switch to its opposite state. Transistors M4 and M5 therefore must be very large transistors in order to deliver that much current, and therefore must have large gate capacitances. The required large gate capacitances of current mirror output transistors M4 and M5 undesirably limit the achievable speed/propagation delay of comparator 1 of Prior Art FIG. 1.
A certain amount of hysteresis usually is desirable in a comparator. One way to obtain hysteresis in comparator 1 is by means of above-mentioned transistors M6 and M7. The amount of hysteresis is determined by the area ratio of transistors M3 and M7, which is the same as the area ratio of transistors M2 and M6. The amount of hysteresis is determined by positive feedback, so latch circuit M8/M9 will not switch from its present state to its opposite state until the drain current of one of input transistors M0 and M1 increases sufficiently and the drain current of the other input transistor decreases sufficiently. Because of the positive feedback, latch circuit M8/M9 can not switch its state until the ratio of the drain currents in transistors M3 and M7 is such that they can “overpower” the current mismatch caused by the positive feedback that is determined by the area ratio of transistors M3 and M7. (The two foregoing ratios need to be kept nearly constant in order to prevent latch circuit M8/M9 from switching states.)
For example, if VIN+ increases relative to VIN− so that there is a particular amount of current in input transistor M1 and the same amount of current flows in current mirror output transistor M3, it means that input transistor M0 provides less current than hysteresis transistor M7 (assuming hysteresis transistor M7 is matched to current mirror reference transistor M3). Comparator 1 will not able to switch to its opposite state because transistor M7 in effect short-circuits the gate of current mirror input transistor M2 to VDD. Therefore, there is no current in transistor M6, the current flow being through transistors M3 and M7. Consequently, latch circuit M8/M9 can switch state only if the amount of current in transistor M0 exceeds the current in transistor M7. Transistors M3 and M7 may be ratioed so as to cause more current to flow through input transistor M0, thereby turning on current mirror reference transistor M2 by increasing the ratio of the current in transistor M0 to the current in transistor M1. This is because the ratio of the current in current mirror reference transistor M3 to the current in hysteresis transistor M7, which also is the ratio of the current in current mirror reference transistor M2 to the current in hysteresis transistor M6, determines the ratio of the currents in input transistors M0 and M1 at the times at which switching of latch M8/M9 occurs, thereby resulting in input-related voltage hysteresis in comparator 1.
It would be highly desirable to keep current mirror output transistors M4 and M5 small to minimize the amount of capacitance that must be charged proportionately to tail current ITAIL and thereby achieve a low comparator propagation delay while also maintaining a low power consumption of the comparator, but unfortunately comparator 1 of Prior Art FIG. 1 does not permit this to be accomplished. Comparator 1 of Prior Art FIG. 1 inherently requires that current mirror output transistors M4 and M5 be able to generate relatively large currents in order to switch the state of latch M4,M5. Consequently, a relatively large minimum value of ITAIL is required, and therefore comparator 1 consumes a relatively large amount of current and power.
Thus, there is an unmet need for a comparator capable of “on the fly” adjustment of both comparator speed/propagation delay and comparator power consumption according to system needs.
There also is an unmet need for a comparator capable of switching and latching its state without requiring a large tail current source in a differential input stage of the comparator.
There also is an unmet need for a comparator which is capable of “on the fly” adjustment of both comparator speed/propagation delay and comparator power consumption according to system needs and which also is capable of switching and latching the state of the comparator without requiring a large tail current source in a differential input stage of the comparator.
There also is an unmet need for a comparator configuration that is optimal or near-optimal for a wide range of applications.
There also is an unmet need for a comparator configuration which requires very little design effort to adapt it for a wide range of applications.